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Design Security Feature
Cyclone III LS devices offer the following design security features:
■ Configuration security using advanced encryption standard (AES) with 256-bit
volatile key
■ Routing architecture optimized for design separation flow with the Quartus® II
■ Design separation flow achieves both physical and functional isolation
between design partitions
■ Ability to disable external JTAG port
■ Error Detection (ED) Cycle Indicator to core
■ Provides a pass or fail indicator at every ED cycle
■ Provides visibility over intentional or unintentional change of configuration
random access memory (CRAM) bits
■ Ability to perform zeroization to clear contents of the FPGA logic, CRAM,
embedded memory, and AES key
■ Internal oscillator enables system monitor and health check capabilities

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