original and new integrated circuits electronic components DSPIC33FJ256GP710-I/PF

datasheet

  • Modified Harvard architecture
  • C compiler optimized instruction set
  • 16-bit wide data path
  • 24-bit wide instructions
  • Linear program memory addressing up to 4M instruction words
  • Linear data memory addressing up to 64 Kbytes
  • 83 base instructions: mostly 1 word/1 cycle
  • Sixteen 16-bit General Purpose Registers
  • Two 40-bit accumulators:- With rounding and saturation options
  • Flexible and powerful addressing modes:- Indirect, Modulo and Bit-Reversed
  • Software stack
  • 16 x 16 fractional/integer multiply operations
  • 32/16 and 16/16 divide operations
  • Single-cycle multiply and accumulate:- Accumulator write back for DSP operations- Dual data fetch• Up to ±16-bit shifts for up to 40-bit data

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