Electronic Component Integrated Circuits (ICs) PCI2050BIZHK

datasheet

Features
The PCI2050B bridge supports the following features:
Two 32-bit, 66-MHz PCI buses
3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
Internal two-tier arbitration for up to nine secondary bus masters and supports an external secondary bus
arbiter
Ten secondary PCI clock outputs
Independent read and write buffers for each direction
Burst data transfers with pipeline architecture to maximize data throughput in both directions
Supports write combing for enhanced data throughput
Up to three delayed transactions in both directions
Supports the frame-to-frame delay of only four PCI clocks from one bus to another
Bus locking propagation
Predictable latency per PCI Local Bus Specification
Architecture configurable for PCI Bus Power Management Interface Specification
CompactPCI hot-swap functionality
Secondary bus is driven low during reset
VGA/palette memory and I/O decoding options
Advanced submicron, low-power CMOS technology
208-terminal PDV, 208-terminal PPM, or 257-terminal MicroStar BGA package

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